INTERFACING OF EEPROM with 8051

7.1 Introduction

As we know, ROM is a memory that does not lost its contents when the power is turned off. For this reason ROM is also called Non-Volatile Memory. There are different types of ROM such as PROM, EPROM, EEPROM, Flash EPROM and Mask ROM. In which PROM refers to the Kind of ROM that the user can burn information into. PROM is a user programmable memory. PROM is referred to as OTP (One time programmable). EPROM was invented to allow making changes in the contents of PROM after it is burned. In short, one can program the memory chip and erase it thousands of time. This is especially necessary during development of microcontroller based project. EEPROM is electrically erasable programmable ROM. EEPROM has several advantages over EPROM. EEPROM does not require external eraser and programming device. Flash EPROM has become a popular user programmable memory chip. The reason behind that is the eraser of entire content takes less than a second that why it is named Flash memory. When flash memory contents are erased the entire device is erased whether in EEPROM one can erased a desired section or byte. In masked ROM, the contents are programmed by the IC Manufacturer. It is not a user programmable ROM. Masked ROM is used when the needed volume is high and the contents will not change. It is cheaper than other kind of ROM.

7.1.1 FEATURES:-

1.      1000000 erase/write cycle’s minimum with over 10 year’s data retention.

2.      Single 3V to 5.5V supply voltage.

3.      Two wire serial interface, fully I2C BUS compatible.

4.      Byte and multi byte write (up to 4 bytes) Page write (up to 8 bytes).

5.      Byte, random and sequential read modes.

6.      Self timed programming cycle.

7.      Automatic address incrementing

7.2  Pin Description

AT24c02 provides bits of serially erasable and programmable Read Only memory (EEPROM) organized as 256 words of 8-bits each. The device is optimized to be used in many industrial and commercial applications where low power and low voltage operation are essential. 24c02 EEPROM IC is available in 8-pin DIP and is accessed via two-wire serial Interface. Figure shows pin Description of 24c02 EEPROM IC.

   SERIAL CLOCK (SCL):

The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

  SERIAL DATA (SDA):

The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.

 DEVICE/PAGE ADDRESSES (A2, A1, A0):

The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).

WRITE PROTECT (WP):

The AT24C02 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in Table 2. WP pin status Part of Array Protected 24c02 .At VCC Full (2K) Array. At GND Normal Read/Write Operations

The ST24C02A is a 2k bit electrically erasable programmable memory, organized as 256x8 bits. The memory is compatible with the I2C bus standard, two data bus and serial clock. The STA240C2A carries a built in a bit unique device information code corresponding to the I2C bus definition. This is used together with a 3-bit chip enable input to form a 7-bit memory select signal. In this way up to 8 ST24C02A’S may be connected to the I2C bus and selected individually. The ST24C02A behaves as a slave device in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by start condition generated by the bus master. The start condition is followed by a stream of 7 device select bit plus one read/write bit and terminated by an acknowledge bit. When writing data to the memory it respond to the 8 bits received by asserting an acknowledge bit during the ninth bit time. Data transfers are terminated with a stop condition.

7.3OPERATING MODES:-

There are both read and write modes. Each is entered by the correct sequence of serial bits sent to the device on the SDA line. For some write modes the status of the mode input is also used to set the operating mode. The 8 bits sent after a start condition are made up of a bits that identify the device type, 3 chip enable bits and one direction indicator bit. Whether the controller wants to read from the device or write to the device is decided by the very first byte sent to it on the SDA line. The last bit of very first sent to E2PROM is directional indicator. If this bit is ‘Zero’ the direction of data flow is from controller to the E2PROM and if ‘One’ it is from E2PROM to the controller. Following are the different modes for reading or writing from the E2PROM.

 1). Byte Write: - In this mode a device select is sent with the R/W bit at ‘0’ followed by the address of the byte. This is followed by the 8 bit data to be written during the programming cycle.

2). Multi byte Write And Page Write: - In these modes up to 4 or 8 bytes respectively may be written in one programming cycle. Multi-byte write mode is activated when the mode pin is at V/H level and page write when mode is at V/L. A device select is sent with the R/W bit at ‘0’ followed by the data bytes to write. The bytes are written in the programming cycle 8 bytes written in the page write mode must have the same five upper address bits

3). Current Address: In this mode device select is sent with the R/W bit at ‘1’. The address of various byte accessed is automatically incremented and the new byte read.

4). Random Address Read: - This mode allows random access to the memory. A device select is sent with R/W bit at ‘0’ (write) followed by the address. Then a new start condition is forced with the same device select is sent with the R/W bit at ‘1’ (read) and the byte is read.

5). Sequential Read: - This mode starts with either a current address or random address read sequence it reads consecutive bytes as long as the bus master acknowledges each one without generating a stop condition.

7.4 Device operation based on I2c protocol:

The 24C02 family uses two I/O lines for interfacing: SCL (Serial Clock) and SDA (Serial Data). SCL edges have different functions, depending on whether a device is being read from or written to. When clocking data into the device, the positive edges of the clock latch the data. The negative clock edges clock data out of the device. The SDA signal is bi-directional, and is physically an open-drain so that multiple EEPROMs or other devices can share the pin. Both SCL and SDA must be pulled high externally. The protocol used by the EEPROM is based in part on an ACK (acknowledge) bit sent by the EEPROM, if the data sent to it has been received. All addresses and data are sent in 8-bit words. The EEPROM sends the ACK as a low bit period during the ninth clock cycle. The EEPROM looks for specific transitions on the SCL and SDA pins to qualify READ and WRITE. Data on the SDA pin may change only during the time SCL is low. Data changes during SCL high periods indicate a START or STOP condition. A START condition is a high-to-low transition of SDA with SCL high. All data transfers must begin with a START condition. A STOP condition is a low-to-high transition of SDA with SCL high. All data transfers must end with a STOP condition. After a READ, the STOP places the EEPROM in a standby power mode. Refer to Figure 1 for START and STOP conditions. Figure 1. START and STOP conditions.

Device Addressing

The 24C02 has 3 physical pins, designated A2, A1, and A0, which are tied to logic 1 or 0 levels. This allows eight unique hardware addresses, so that up to eight 24C02s can share the SCL and SDA lines without conflict. There is an internal address comparator that looks for a match between the address sent by the master controller and the 24C02's unique 7-bit address, determined in part by A2, A1, and A0. Refer to Table 1below. Table 1. 24C02 Device Address

MSB LSB

1 0 1 0 A2 A1 A0 R/~W

The device address is sent immediately after a START condition. The first four bits are the sequence "1010", which is a simple "noise filter" which prevents a random noise burst on the lines from accessing the device. The last bit sent is a 1 for READ and a 0 for WRITE. The code example below is for random READ/WRITE operations. The part can also perform Page Write/Sequential Read with slight code modifications. See the 24C02 data sheet for more information.

Byte Write to Memory: The Byte Write sequence is shown in Figure 2. After receiving a START condition and a device address, the EEPROM sends an ACK if the device address matches its own unique address. The MAX7651 waits for the ACK and aborts communication if it is not present. Next, an 8-bit byte address is sent, followed by another ACK. The MAX7651 then sends the 8-bit data byte, waits for the third ACK, and sends a STOP condition.

WRITE operation.

It is important to note that after the STOP condition is received, the EEPROM internally waits for the data to be stored into its internal memory array. This can take as long as 10ms. The 24C02 will ignore attempted accesses while the internal EEPROM is being programmed. The part can be polled for completion of the internal write cycle. This involves sending another START condition (also called a REPEATED START), followed by the device address byte. Note, in this case, there is no STOP condition sent. The EEPROM will send an ACK if the internal programming cycle is completed. The MAX7651 can also be programmed to wait 10ms before proceeding.

Byte Read from Memory

Reading a byte from the 24C02 EEPROM at a random address requires that a dummy WRITE operation be performed before the READ. See Figure

The sequence is:

• START condition

• Send device address with R/~W = 0 'dummy WRITE' command

• Wait for ACK

• Send byte memory address

• Wait for ACK

• Send REPEATED START condition

• Send device address with R/~W = 1 (READ command)

• Wait for ACK

• Read the 8 data bits into the MAX7651, MSB first

• No ACK

• STOP condition

This sequence is quite involved! The total number of SCL transitions required for a READ is 38.

Waveform for data

7.5 Hardware connection

EEPROM is based on i2c protocol ,two wired serial protocol. For that we need two pins. We use p3.6 for SCL and p3.7 for SDA . a0,a1,a2 are address lines to select EEPROM chip. That is hard wired and fix for each EEPROM. To send address, data, start-stop condition data we use SCL and SDA.